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Ansys cloud – native solutions provide unparalleled capability to speed up completion times for even the largest finFET integrated circuits (IC) and 3D/.5D multi-die systems. These powerful multi-physics analysis and verification tools reduce power consumption, improve preformation, improve and reliability, and lower project risk with foundry-certified golden signoff verification.
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Features
Power integrity (EM/IR) analysis and modeling with RedHawk-SC for digital, and Totem-SC for analog designs Electrothermal analysis of 2.5D/3D multi-die systems Variability-aware path timing with Path FX Electrostatic discharge (ESD) and reliability analysis with PathFinder-SC RTL power analysis and reduction with PowerArtist On-silicon electromagnetic analysis and modeling with RaptorH, Pharos, Exalto, and VeloceRF Cloud-native elastic compute architecture for full-chip capacity helloooo |
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Products
Golden IR-drop signoff verification for digital designs Electromigration reliability signoff Timing impact of dynamic voltage drop aggressors High-capabilities cloud-native infrastructure Advanced power analytics and build quality metric Foundry certified for all finFET to 3mm Redhawk-SC option for 3D/.5D chip-package co-analysis Power integrity analysis for coupled chip-package system Thermal simulation Identifies thermal-mechanical stress Comprehensive early prototyping features Integrated with board/system analysis tools Power integrity and noise verification at transistor level Capacity for several million xtor flat Simultaneous simulation of digital and analog blocks Abundant what-if scenarios Incremental analysis Creates IP power models for the use with RefHawk-SC Electrostatic discharge (ESD) integrity simulation Current density checks Layout level and netlist level analysis Integrated extraction and simulation engine Foundry-certified silicon correlation Capacity to analyze full SoCs Analyzes DvD-aware timing variability Critical path timing variability and clock tree analysis Single standard cell timing model for any voltages SPICE accurate results without voltage interpolation High capacity, fast and SPICE accurate Complements STA |
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Products
RTL design-for-power platform Analysis-driven power reduction Physically aware RTL power budgeting Long vector profiling Direct links to hardware emulators Electromagnetic on-silicon modelling Includes gold standard HFSS engine High capcailty and linear multi-CPU scalability S-param and RCLk parasitic extraction Models power grids, clock trees, spirals, MiM/MoM caps, etc Foundry certified and silicon correlated Identifies nets susceptible to electromagnetic (EM) crosstalk Includes substrate coupling Ranks EM aggressors per victim net SoC and large block capability What-if capability with point-and-click GUI RLCk signoff extraction tools (post-LVS) Models electrical, magnetic and substrate coupling Highly reduce lumped-element models Complements digital RC extractors Extract entire SoC power grid in minutes What-if-capability with point-and-click GUI Synthesis and modelling of indicators, transformaers and transmission lines Creates DRC/DFM clean devices Silicon verified upto 110 GHz S-param and compressed RCLk models Generates parameterized PCell/Pycells |